A conventional computer system may include a first chip coupled to a second chip via a link (e.g., through a chip input/output (I/O) interface) that may, for example, be one to six bytes wide. While the conventional computer system operates in a test mode, the first chip may generate a known bit pattern and transmit the bit pattern to the second chip via the link. Additionally, the second chip may store bits of the known bit pattern in a buffer. After the second chip receives each bit of the bit pattern via the link, the bits may be compared via compare logic against corresponding bits of the known bit pattern stored in the buffer of the second chip. If all bits of the bit pattern received in the second chip via the link match respective bits of the known bit pattern stored in the buffer, the link and first and second chips may be deemed not faulty. Alternatively, if one or more bits of the bit pattern received in the second chip via the link do not match respective bits stored in the buffer, the link, first chip and/or second chip may be faulty. In this manner, the link, first chip and second chip may be tested. However, such a testing method requires the second chip to include additional logic (e.g., the buffer and/or compare logic), and therefore, inefficiently consumes chip area.
Accordingly, improved methods and apparatus for testing a link are desired.